Hi , all.
I have this doubt.
The BIST works with a internal reset at the end of the test.
In our project we are using the approach described by NXP for MC33908.
Having the reset, the FCCU_0, FCCU_1 will be drived by external pull-up, pull-down resistor into Error condition for SBC. The SBC will produce a reset (external reset) for the MCU. The result is that we loose possibility to read result of BIST ON LINE test.
How is possible solve this issue?
Is a solution try to perform BIST without scheduling final reset?
Thanks into advance, for all answer.