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Question asked by Maurizio Greco on Sep 27, 2018
Latest reply on Oct 3, 2018 by Maurizio Greco

Hi , all.


I have this doubt.

The BIST works with a internal reset at the end of the test.

In our project we are using the approach described by NXP for MC33908.

SBC with MPC5777C

Having the reset, the FCCU_0, FCCU_1 will be drived by external pull-up, pull-down resistor into Error condition for SBC. The SBC will produce a reset (external reset) for the MCU. The result is that we loose possibility to read result of BIST ON LINE test.


SBC and Reset


How is possible solve this issue?

Is a solution try to perform BIST without scheduling final reset?

It's a solution do not use the pull up on FCCU_1 (use a pull down) and do not use a pull down on FCCU_0 (use a pull up) ?SBC bi-stable protocol

Thanks into advance, for all answer.