Thanks again for your previous help.
We were wondering if it is necessary to post every question we have to the NXP forum or can we send them directly to you or another NXP engineer?
We have been designing with Microprocessors for 30 years (10 with NXP MCUs) and are used to dealing with dedicated pins. We usually can figure out the design of a new Microprocessor with little or no help from the MCU engineering support team. However, we are a little confused by the amount of muxed and shared pins on the new crossover processors. For example, SEMC_ADDR8 –> CS5 is used to chip select the 256Mb NOR flash as you explained below. However, it will also be used as address line A8 when we address our SDRAM with the SEMC controller. Doesn’t that mean that the flash will get chip selected sometimes when we are accessing the SDRAM and ADDR8 is used? Do we need to qualify the Flash CS5 chip select somehow?
Also, we are booting off of the parallel NOR Flash. Section 8.6 in the reference manual (see below) states that when booting off the NOR flash, chip select CS0 is used. We are using CS5. Do we need to gate them together? Wii it will use CS0 initially and then change to using CS5 after configuration? We have found that the LPC3240 User Manual explains things in greater detail and more clearly than the RT1050 Reference Manual does even though it is 2000 less pages. Is there any new documentation being planned?
8.6 Boot devices (internal boot)
The chip supports these boot flash devices:
• Serial NOR flash via FlexSPI Interface
• Serial NAND Flash via FlexSPI Interface
• Parallel NOR flash with the Smart External Memory Controller (SEMC), located on CS0, 16-bit bus width.
i.MX RT1050 Processor Reference Manual, Rev. 1, 03/2018