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PF1550 increase OTP_POR_DLY

Question asked by Victor Pecanins on Sep 23, 2018
Latest reply on Dec 11, 2018 by Jose Alberto Reyes Morales



I'm designing a custom board with i.MX6 ULL & PF1550A6.According to datasheet:


At the end of the power-up sequence, the signal RESETBMCU is deasserted some time after the last regulator is brought up (time slot 3 for the A6 version). The delay of the reset signal is set by the register POR_DLY, that is loaded from the OTP memory register OTP_POR_DLY. In all the possible options, the PMIC is shipped with OTP_POR_DLY=2ms:

RESETBMCU is pulled high 2.0 ms to 1024 ms after the last regulator powers up. This
delay is OTP programmable through the OTP_POR_DLY[2:0] bits.

Now, the problem is, I find this time is a bit short and I want to increase it to at least 128ms, to allow the capacitors from  VDD_ARM_CAP & VDD_SOC_CAP to be fully charged before the CPU is released from RESET.


In the reference design, this problem is solved adding a reset supervisor, UM803RS, but I want to avoid using more external ICs and do it all with the PMIC.


The question is: How can I program the OTP_POR_DLY to 128ms? According to datasheet this should be possible, but it's not documented:

OTP (One time programmable) memory for device configuration
– User programmable start-up sequence, timing, soft-start and power-down sequence
– Programmable regulator output voltages and charger parameters

Thanks and best regards,