Seth Appleman

5485EVB - DSPI controller initialization

Discussion created by Seth Appleman on Dec 4, 2008
Latest reply on May 26, 2009 by ian lovatt
I need help setting up the DSPI controller. I have my 5486 mounted on a demo board that runs DSPICS0, DSPISIN0, DSPIOUT0, DSPISCK to an external SD card.
 
I'm setting the config register and timer attributes register as follows:
 
MCF_DSPI_DMCR |= (0x80000000 | //31 MSTR: DSPI is in master mode
       0x40000000 | //30 CSCK: continuous DSPISCK enabled
       0x00000000 | //29-28 DCONF: SPI configuration
       0x08000000 | //27 FRZ: halt serial transfers
       0x00000000 | //26 MTFE: modified SPI transfer format disabled
       0x02000000 | //25 PCSSE: DSPICS5/PCSS used as ~PCSS peripheral strobe signal
       0x01000000 | //24 ROOE: RX FIFO overflow overwrite enable
       0x00010000 | //bit 16 CS0 inactive high
       0x00000000 | //13 DTXF: TX FIFO enabled
       0x00000000 ); //12 DRXF: RX FIFO enabled
      
 //DSPI clock and transfer attributes register 0 (DCTAR0)
 MCF_DSPI_DCTAR0 |= (0x07800000 | //30-27 TRSZ: tansfer size 16 bits
      0x00000000 | //26 CPOL: clock polarity (inactive low)
      0x02000000 | //25 CPHA: clock phase (data changed on leading edge of DSPISCK and captured on following edge)
      0x00000000 | //24 LSBFE: data is transferred MSB first
      0x00000000 | //23-22 PCSSCK: CS to SCK prescaler (1 clock prescaler)
      0x00000000 | //21-20 PASC: after DSPISCK delay prescaler (1 clock negation)
      0x00000000 | //19-18 PDT: delay after transfer prescaler (1 clock delay)
      0x00000000 | //17-16 PBR: baud rate prescaler (2 clock prescaler)
      0x00000000 | //15-12 CSSCK: CS to SCK delay scaler (0x0 -> 2 delay scaler val)
      0x00000000 | //11-8 ASC: after SCK delay scaler (0x0 - > 2 delay scaler val)
      0x00000000 | //7-4 DT: delay after transfer scaler (0x0 -> 2 delay scaler val)
      0x00000007 ); //3-0 BR: baud rate scaler (0x7 -> 128 scaler value)
 
When I throw a byte into the TX queue and flush the queue to send it out, I am not getting a transfer complete flagged in bit 31 of the status register. However, the TX fifo has no data elements in it. Any ideas?

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