When using LPC1778 with 32-bit External Memory interface,
(refer to cmsis-RTOS)
CS / OE selection interval is set to 60ns, but the actual operation is doubled with 100ns.
CS & OE ENABLE Interval timing is 2times longer than Address & Data.
How to reduce these CS & OE ENABLE interval timing such as Address/Data interval length?
(CS : Green, OE : Yellow, Addr : violet, DATA : Blue)
in order to operate same interval length exactly between CS/OE and Address/Data.
It's occurred address changing(0 ->1 : Blue circle) due to 2-times longer interval length.
How to change such as RED line in drawing signal waveform attached?
1. Issues :
1) CS3 setting value is set to operate at about 60ns as shown below, but 100ns actually appears
2) ADDR changes while maintaining CS3 LOW (CS is changed once after 60ns in 120ns interval)
3) When CS3 is output as 120ns, it is outputted as 60ns every 16th.
2. Reference :
CS related setting value
* PB = 1
3. look at the Timing diagram as below, there are four RD5s,
Which is the standard? or What is the standard?