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HDMI Pixel clock frequency 170000 kHz is not supported

Question asked by Alex Soo on Sep 17, 2018
Latest reply on Oct 12, 2018 by Quyen Ngo

Hi there,

On my side, I noticed an issue that when booting up an IMX8MQ EVK board with a Yocto Linux image of kernel version 4.9.88 programmed into an SD card, there is no video output from the HDMI interface, and running the command “dmesg” shows below kernel error messages:

[    8.253446] [drm] mode:1920x1080p75, pixel clock 170000 kHz

[    8.259248] [drm] Pixel clock frequency: 170000 kHz, character clock frequency: 170000, color depth is 8-bit.

[    8.269686] [drm:phy_cfg_t28hpc] *ERROR* This pixel clock frequency (170000 kHz) is not supported.

[    8.279044] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock

[    8.285869] [drm:imx_hdp_bridge_mode_set] *ERROR* Failed to initialise HDP PHY

 

The pixel clock frequency of 170000 kHz is read from the EDID inside the display monitor connected to the HDMI interface of the IMX8MQ EVK board,

[    9.638122] i.mx8-hdp 32c00000.hdmi: imx_hdp_connector_get_modes: 0,ff,ff,ff,ff,ff,ff,0

[    9.638125] imx_hdp_connector_get_modes: EDID version 1.3

[    9.643636] imx_hdp_connector_get_modes: detailed timing 0 pixel clock 170000 khz

[    9.651285] imx_hdp_connector_get_modes: detailed timing 0 horizontal active 1920 pixels

[    9.659490] imx_hdp_connector_get_modes: detailed timing 0 vertical active 1080 pixels

[    9.667628] imx_hdp_connector_get_modes: detailed timing 1 pixel clock 148500 khz

[    9.675222] imx_hdp_connector_get_modes: detailed timing 1 horizontal active 1936 pixels

[    9.683425] imx_hdp_connector_get_modes: detailed timing 1 vertical active 1080 pixels

[    9.691458] imx_hdp_connector_get_modes: detailed timing 2 pixel clock 0 khz

[    9.698672] imx_hdp_connector_get_modes: detailed timing 3 pixel clock 0 khz

 

The pixel clock frequency 170000 kHz is currently not supported in the HDP PHY initialization function when pixel_clk_from_phy == 1.  Besides, it looks like the following list of pixel clock frequencies are possibly not supported by the driver also:  119MHz, 88.75MHz, 108MHz, 71MHz, 40MHz, 36MHz, 30.24MHz, 25.175MHz, 28.32MHz, 75MHz, 65MHz, 148.352MHz, 27.027MHz, 74.176MHz, 25.2MHz, 74.176MHz, and 185.580MHz

 

To verify the functionality of the HDMI video output, the only workaround I can think of is to modify the pixel clock frequency to a supported frequency 148.5MHz before calling the hdmi_phy_init_t28hpc() function, and then the HDMI video output is working properly.

 

In the function imx_hdp_mode_setup(),

 

/* mode set */  

mode->clock = 148500;     < ============

ret = imx_hdp_call(hdp, phy_init, &hdp->state, mode, hdp->format, hdp->bpc);

if (ret < 0) {

        DRM_ERROR("Failed to initialise HDP PHY\n");

        return;

}

imx_hdp_call(hdp, mode_set, &hdp->state, mode,

             hdp->format, hdp->bpc, hdp->link_rate);

 

Currently, we are looking for a way to support pixel clock frequency of 170MHz and 185.58MHz for our monitors, and I think it's required to update the function phy_cfg_t28hpc() in file API_AFE_t28hpc_hdmitx.c 

 

However, we do not know how to work with the registers: cmnda_pll0_ip_div, cmn_ref_clk_dig_div, pll_feedback_divider_total, cmnda_pll0_fb_div_*, cmnda_hs_clk_*

 

Is there any guidelines, documentations, or specifications that can help?

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