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LPC4357 bad EMC read access

Question asked by Robert Morrison on Sep 14, 2018
Latest reply on Nov 5, 2018 by Herbert Lu

I have been programming the nxp lpc4357 processor on a custom board for a couple of years without problems, but recently I seem to have encountered a read access problem using the EMC port pins.  I have address 0x1c000000 configured as an 8 bit interface that talks to an 8 bit interface on an FPGA.  I traced back a read access failure to the port pins, where a single character read (verified by looking at the assembly ldrb instruction) is showing that the address is changing in the middle of this access.  This wouldn't necessarily cause a failure (two consecutive address byte reads) except that the data from the second half is getting loaded rather than the data from the address in question.  Here is the configuration of the static memory read EMC registers:


   LPC_EMC->CONTROL  = 0x00000001;   // turn off EMC reset
   LPC_EMC->STATICCONFIG0  = 0x00000080;   // set for 8 bit bus, enable nwe
   LPC_EMC->STATICWAITRD0  = 0x00000005;   // 5 cycle wait states
   LPC_EMC->STATICWAITPAG0 = 0x00000001;
   LPC_EMC->STATICWAITWR0 = 0x00000003;    // must be set to 3 (31ns)
   LPC_EMC->STATICWAITTURN0 = 0x00000001;   // 1 cycle turnaround


Here is the test code that reproduces the problem in the actual code:

   result_read = *(char *)(0x1c000028);


The result_read actually contains the data from 0x1c000029.


I've attached a waveform that shows the unexpected address change in the middle of a read cycle.  If I set that access to a word 16 bit address, it does the same thing for two cycles--four consecutive addresses.  It's acting like some kind of page mode is running, but even there it doesn't store the data in the right locations.  (Note that I have the page mode bit in the STATICCONFIG0 register turned off).  I attached a waveform that shows the EMC_a0 line changing in the middle of the read access.


Why am I seeing this behavior?