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Question asked by David Gabbay on Sep 14, 2018
Latest reply on Oct 1, 2018 by Pavel Chubakov

My question are related to the MPC870.

  1. Is s/w watchdog reset reflected on the HRESET* pin? My observations show it is not but the reset process is carried out. I would like your confirmation.
  2. The above question follows behavior depicted on the attached picture. I see HRESET* asserted (for unknown reason at this point). The boot process starts but soon the HRESET* asserted again. this scenario repeats itself several times and eventually the HRESET* stays asserted until I (manually) power it up. As said, I do not know what cause the reset at the middle of of work (under investigation, likely h/w issue). Has somebody encountered this scenario or has explanation for this.
  3. In order to generate check-stop case I did the following:
    Setting PLPRCR[CSR] bit.
    Clearing MSR[ME] bit.
    Clearing MSR[DR] bit (to avoid MMU exception).
    Access none-existing address.

I have experienced check-stop but the RSR[SWRS] was set rather than RSR[CSRS], meaning the s/w watchdog took the lead. If I repeat the above steps after disabling the the s/w watchdog the device was halted but no reset followed. Any idea?


Thank You