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i.MX6ULL DDR calibration results

Question asked by Ofer Austerlitz on Sep 12, 2018
Latest reply on Sep 13, 2018 by igorpadykov


I'm using the i.MX6ULL_DDR3_Script_Aid_V0.01 init script and the ddr_stress_tester_v2.90 to perform calibration for the iMX6ULL SoC with DDR of 8Gb density with dual CS.
after calibration has finished,I recive 6 registers to update vlaues for:

MMDC registers updated from calibration

Write leveling calibration
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001C001C

Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x01480154
MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000

Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x40402C30

Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x4040403C

Success: DDR calibration completed!!!

The following 2 registers:
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001C001C
MPDGCTRL1 PHY0 (0x021b0840) = 0x00000000 (value is always 0)


do not appear in the I.MX6ULL_DDR3_Script_Aid_V0.01 init script nor do they appear in NXP's board .cfg file:

They do appear however now in the register list section "35.12 MMDC Memory Map/Register Definition" of the i.MX 6ULL r Reference Manual.

Should these registers be added to my board file as well or this is a bug of the tool i.e. relevant to other SoCs but not to iMX6ULL?

would appreciate your clarification on this.