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imx6sx custom DP83867 ethernet PHY not working

Question asked by Mahtab Sarwar on Sep 13, 2018
Latest reply on Oct 5, 2018 by Mahtab Sarwar

Hi there,

 

We have an imx6sx in a custom board with 2 ethernet phys: one is a TI DP83867 and one is an NXP TJA1100 automotive phy. The design is based on the Sabresd dev board. I have a problem configuring the mdio bus to recongnize both phys. The TJA1101 is always seen on the bus but the DP isn't. The TJA1101 uses RMII mode and the DP uses RGMII mode. The phy side of the dp is fine; clocks to the DP are fine - 25MHZ because it's limited to 100Mbits; the DP driver is in the kernel; the activity led bursts into life both ends when a cable is connected; the DP is recognized in u-boot as eth0 [ PRIME ] ( I had to change the mask in fec_phy_init function in fec_mxc.c, because the phy id is 0x1f ). However, linux cannot find the phy and doesn't load the driver ! The mdio bus cannot see the DP phy but can see the TJA1101.

 

The schematics are:

 

DP83867:

 

TJA1100:

 

 

 

 

the device tree is based on the mx6sx-sdb and looks like this:

imx6sx.dtsi:
  fec1: ethernet@02188000 {
      compatible = "fsl,imx6sx-fec", "ethernet-phy-ieee802.3-c22";
      reg = <0x02188000 0x4000>;
      interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
      <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&clks IMX6SX_CLK_ENET>,
      <&clks IMX6SX_CLK_ENET_AHB>,
      <&clks IMX6SX_CLK_ENET_PTP>,
      <&clks IMX6SX_CLK_ENET_REF>,
      <&clks IMX6SX_CLK_ENET_PTP>;
      clock-names = "ipg", "ahb", "ptp",
      "enet_clk_ref", "no_enet_out";
      fsl,num-tx-queues=<3>;
      fsl,num-rx-queues=<3>;
      stop-mode = <&gpr 0x10 3>;
      fsl,wakeup_irq = <0>;
      phy-id=<0x2000a231>;
      status = "okay";
};

fec2: ethernet@021b4000 {
      compatible = "fsl,imx6sx-fec";
      reg = <0x021b4000 0x4000>;
      interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
      clocks = <&clks IMX6SX_CLK_ENET>,
      <&clks IMX6SX_CLK_ENET_AHB>,
      <&clks IMX6SX_CLK_ENET_PTP>,
      <&clks IMX6SX_CLK_ENET2_REF_125M>,
      <&clks IMX6SX_CLK_ENET_PTP>;
      clock-names = "ipg", "ahb", "ptp",
      "enet_clk_ref", "no_enet_out";
      fsl,num-tx-queues=<3>;
      fsl,num-rx-queues=<3>;
      stop-mode = <&gpr 0x10 4>;
      fsl,wakeup_irq = <0>;
      status = "disabled";
};

 

custom board dtsi:

 

&fec1 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_enet1>;
   phy-mode = "rgmii";
   phy-handle = <&ethphy0>;
   fsl,magic-packet;
   status = "okay";

   mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            ethphy0: ethernet-phy@1 {
               compatible = "ethernet-phy-ieee802.3-c22";
               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
               ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
               reg = <1>;
            };

 

            ethphy1: ethernet-phy@2 {
               compatible = "ti,tja1101";
               reg = <2>;
            };
      };
};

 

&fec2 {
   pinctrl-names = "default";
   pinctrl-0 = <&pinctrl_enet2>;
   phy-mode = "rmii";
   phy-handle = <&ethphy1>;
   status = "disabled";
};

 

pin muxing is as follows:

 

pinctrl_enet1: enet1grp { fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
>;
};

 

pinctrl_enet2: enet2grp {
fsl,pins = <
   MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x10b0
   MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
   MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
   MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
   MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
   MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
   MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
   MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
   MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
   MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
   MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};

 

My questions are: is the configuration - especially the device tree - correct ? Why can't the mdio driver recognize the dp chip on the bus ? Even when the TJA1101 is held in reset, it still registers on the mdio bus and but mdio can't find the DP, despite the phy activity light showing the DP working. Does the FEC and mdio allow for the fact that a) both phy's are on the same mdio bus, and b) the DP is in RGMII mode and the TJA1101 is in RMII mode ?


As I understand it, the mdio driver will scan the bus for attached phy's. Does it need to be changed because the phy address of the DP is 0x1f. I also don't understand why the mdio node in the device tree is part of fec 1 but contains both phys, and fec 2 contains the second phy but it still shows up as part of fec 1:

 

Help is greatly appreciated, thanks

 

Mahtab

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