NXP's imx6 development board's DDR layout does not conform to the 3W principle, the spacing between lines is only 4mil.doesn't the board work well?
Would you please provide more information as for what i.MX6 board are you referring to?
The recommendations for Hardware Design for the i.MX6 are on the following document:
From this document clocks or strobes that are on the same layer need at least 2.5× spacing from an adjacent trace (2.5× height from reference plane) to reduce cross-talk. NXP boards should have this spacing albeit not in all DDR signals but rather on clocks and strobe signals.
this board is mx6 dual lite sabre ai cpu card.
As the showed picture,the width of DRAM_A5,A9,A2 is 4.7mil,but the spacing of net A5,A9,A2 is 4mil ,does it OK for DDR?
there is other designs ,every net's sapcing is the 3X of the Cline width.Is it necessary?
It is desirable to follow the 3W rule in all signals, if possible. However, sometimes this is impossible due to space constraints. In those scenarios the absolutely critical signals are clocks and strobes which should at least have 2.5X spacing.
The design looks okay. However, I would recommend giving as much space as possible and testing it after manufacturing. In the final product the manufacturing variations will also affect the design and it's there where you would need to make sure that the DDR works properly. There is a Stress Tool that will surely help:
i.MX6/7 DDR Stress Test Tool V2.92
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