We have in project some issue with DMA and EQADC, first i describe situation:
We are cyclicaly reading one ADC queue of channels (command fifo…), conversion is triggered by EMIOS timer and commands and results are transfered to and from ADC via DMA. Results are saved in cyclical buffer in RAM with 100 samples per channel stored (for some filterin purpouses…).
Now the problem is that in some situations, it looks like one or two channels are skiped during saving results, so value from channel 6 ends up in place of channel 5, ch. 5 in place of ch. 4 etc.
Situations where this happend are with heavy trafic on internal bus (complicated rewriting of some big structures in RAM, stress tests when cache is cyclicaly invalidated…) so i belive it is caused by some prioritization on internal bus.
Originaly we had following setting of XBAR (for slaves RAM and PBRIDGE):
E200z4 (Instruction) M0 : 0
E200z4 (Data/Nexus) M1 : 1
eDMA M4 : 2
When i set DMA to be highest priority and shift acordingly priorities of core (instructions and data..) it solved our problem.
Now, my question is: Is this new setting OK for HW? Can there be some unexpected consequences of this setting?
Thanks for your help