In our current design, we use a 256Mb (32MB) Parallel NOR Flash organized as 16MB x 16bits wide. It contains our boot code, main code and data tables. Our current processor is limited to 16MB per chip select so we use two consecutive memory regions and gate the two chip selects together. We use address lines A0-A22 to address the lower 7FFFFF (8M) shorts along with the second chip select to act as A23 when addressing the upper half.
We are investigating using the crossover i.MXRT1052 Processor in our next design. However, based on our reading of the i.MXRT1050 Processor Reference Manual Rev. 1, 03/2018 we are uncertain if we can address the entire 256Mbits of our NOR flash as we currently do.
It appears Region #5 using Chip Select 5 is designed for booting off a Parallel NOR device. Page 2780 in Chapter 49 of the reference manual states the NOR Flash interface can support up to a 128Mb Flash with only one chip select which would not be big enough for our design. However, in Chapter 6.2 it says that the region can support up to 128Mb per Chip Select implying that you can use multiple chip selects when addressing the Parallel NOR region as you can do in the SDRAM region. This is also implied under the 'Pin Mux in SEMC table' pages 2847-2849 where it shows that SEMC_CSX can be used as A24 and SEMC_CSX can be used as CS5 which would allow us to address the whole chip. Can anyone clear this up for us? Thanks.