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Does T2080 Serdes1 lane2 and lane3 support SGMII protocol?

Question asked by xiongfei liao on Sep 12, 2018
Latest reply on Sep 20, 2018 by xiongfei liao

Hi,

   I have a T2080 board which communicates with FPGA via the SERDES1 lane0,lane1,lane2,lane3 with XAUI protocol, 

I configure the Serdes protocol in RCW as following:

SERDES_PRTCL_1 0x51
SERDES_PRTCL_2 0x1F

where, the SERDES_PRTCL_1 protocol 0x51 was defined in uboot/arch/powerpc/cpu/mpc85xx/t2080_serdes.c(or T2080RM Table 19-1):
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, XAUI_FM1_MAC9, XAUI_FM1_MAC9,
   PCIE4, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },

 

and it was proved working well. 

 

Now I want to configure the last two lanes in Serdes1 as two SGMII ports, I choose the Serdes protocol in RCW as following:

SERDES_PRTCL_1 0x71
SERDES_PRTCL_2 0x1F

where, the SERDES_PRTCL_1 protocol 0x71 was defined in uboot/arch/powerpc/cpu/mpc85xx/t2080_serdes.c(or T2080RM Table 19-1):
{0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
   SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },

 

that is, I configure serdes1 lane2 with SGMII protocol for MAC1, and serdes1 lane3 with SGMII protocol for MAC2. The FPGA partner instances these two serdes lanes as SGMII protocol too, both side disable the Auto-negoation function, but it doesn't work any more.

 

I write a regcmd tool read the MDIO registers, when I disable the AN_EN in register MDIO_SGMII_CR, and disable USE_SGMII_AN in register MDIO_SGMII_IF_MODE, I can measure the differential wave on the Tx_P and Tx_N line.

 

for serdes1 lane2, we use the MAC1 MDIO address 0xE1000 to control the register MDIO_SGMII_CR(0x0) and MDIO_SGMII_IF_MODE(0x14):
regcmd write mdio 0xE1000 phy 0 reg 0 value 0x8340
regcmd write mdio 0xE1000 phy 0 reg 0x14 value 0x9

 

for serdes1 lane3, we use the MAC2 MDIO address 0xE3000 to control the register MDIO_SGMII_CR(0x0) and MDIO_SGMII_IF_MODE(0x14):
regcmd write mdio 0xE3000 phy 0 reg 0 value 0x8340
regcmd write mdio 0xE3000 phy 0 reg 0x14 value 0x9

 

If I enable AN_EN, then I can't measure the differential wave on the Tx_P and Tx_N line.

 

By the way, there is another serdes with SGMII protocol from the T2080 board to FPGA was working well, this SGMII port was coming from a BCM54616S PHY on the T2080 board, which connects to the T2080 EC1(Ethernet Controller 1). The FPGA partner uses the same SGMII Core to instance this serdes lane.

 

Does the T2080 serdes1 lane2 and lane3 support SGMII protocol? How can I configure lane2 and lane3 to work as SGMII port?

 

Any response was appreciated!

Thanks!

 

Felix Liao

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