I am trying to configure the CCI-400 to enable cache coherency.
I have a FPGA writing data to DDR and I am reading it from CPU [A72] in LS1046A.
But the cache does not get updated after the FPGA writes data to it. But if I invalidate the cache inbetween, it works fine.
I see that I am not able to configure any registers of CCI-400 [probably they are secure only registers and uboot leaves me in EL2].
Is there anyway I can check if the CCI works fine and maintain cache coherency.