I'm trying to route a T-Branch topology Address Line on iMX6Q.
The board will be little, and I use 12 layer stack up, (4 sig. layer, 4 gnd layer, 4 Pw layer).
I would like to try to route all the add/cmd signals on an inner layer, but I should have a lot of space between memories chip.
I noted that in the evaluation board MCIMX6Q-SBD the address line it has been divided on two layers. (half line on bottom layer and half on inner layer I do not remember which one).
Could it be a good solution?