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Flex CAN BIT Time and CTRL1 register values for MPC5746

Question asked by Jyothsna Rajan on Aug 31, 2018
Latest reply on Sep 7, 2018 by Jyothsna Rajan


I downloaded the MPC5746R-FlexCAN_wit_interrupts-S32DS_z4_0 example from the MPC5xx examples website . 

The example uses the value 0x01ED0006 for CAN_CTRL1 registers. A comment in the code says the values for the registers bits have been derived using /* CAN bus: 20 MHz clksrc, 500K bps with 20 tq */


Deciphering the register value, the parameters are:


PSEG1 = PSEG2 =5;

RJW = 3



I checked the clock configuration in the example.  

    // AUX_8 clock dividers //
   // FlexCAN clock devider = 5 -> 200MHz/5 = 40MHz
   // Enable divider | divide by 5
   MC_CGM.AC8_DC0.R = 0x80000000 | 0x40000;
   MC_CGM.AC8_SC.B.SELCTL =2; //connect PLL0 on AUX_8

This gives a CAN_CLK is 40MHz. If PRESDIV =1, FSClock = (40/2) or 20MHz. 


I looked at AN1798 but am not able to arrive at the same value of register parameters as used in this example. 


Can someone explain how to arrive at the values used in the example? What bus length and delay parameters  are used?

What does "20 tq" mean - does it mean Nominal Bit Time (Time Quanta per bit) is 20tqs or does it mean that tq(the resolution of FSClock(Can serial clock) ) is 20ns.