- Does the LS1043ARDB support the ARM RAS extension/specification?
- The RAS extensions are part of the ARMv8.2 specification. Does the LS1043ARDB, which is based on the ARMv8.0 specification, support RAS extensions?
- If not is ECC supported by the LS1043ARDB?
- I'm finding the following problem.
When attempting to select the mirror byte function for error injection. ECC_ERR_INJECT[EMB, EIEN]= 0b'11
ECC_ERR_INJECT[EMB,EIEN]=0b'11 cause a hard reset. Also, u-boot board/freescale/ls1043ardb/ddr.c enables ecc_mode popts->ecc_mode=1, but it is unclear from ddr.h if this or any other ECC register is enabled.
Doing the following does a hard reset, but should set EMB and EIEN.
root@ls1043ardb:~# devmem 0x1080E08 w 0x00030000
[ 839.465065] Unhandled fault: synchronous external abort (0x96000210) at 0xff
Then the WDT is triggered and the board resets.
The byte order appears to be correct. If I set the EMB only or the EIEN without EMB set (0x00020000 or 0x00010000), there is no hard reset. Only when I set both the EMB,EIEN (0x00030000) does it do a hard reset.
- I cannot set both at the same time without a hard reset. Why does setting both EMB amd EIEN cause a hard reset?
- What is the purpose of the EMB?
- Is the EMB a test bit to inject the error, even prior to reading and writing a word to a 0x5000 memory location?
- Do I need to set the EMB to cause an ECC error when I write 0x55aa0000 to 0x5000? Not setting EMB does not allow a ECC error when writing and reading 0x5000 with 0x55aa0000.
- So, I have to ask if ECC is supported on the LS1043ARDB?
- Are ARM RAS extensions required for this processor to support ECC?
ECC Mirror Byte.
0b - Mirror byte functionality disabled.
1b - Mirror the most significant data path byte onto the ECC byte.
Error Injection Enable.
0b - Error injection disabled.
1b - Error injection enabled. This applies to the data mask bits, the ECC mask bits, and the ECC
mirror bit. Note that error injection should not be enabled until the memory controller has been
enabled via DDR_SDRAM_CFG[MEM_EN].