Hi All,
I'm referring to the attached ddr init script and could you please help me to fill it correctly ?
My memory is AS4C256M16D3A-12BCN data sheet attached here with.
Processor i.MX6Q
1) What should be the tCL value for this memory ? I can't find it in data sheet.
2) Can you please check this script and tell me whether it is correct or not for my memory module ?
Regards,
Peter.
Hello,
The parameter tCL of the i.MX6 Reference Manual really is CAS Latency, defined as the
delay, in clock cycles, between the internal Read command and the availability of the first
bit of output data. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency (CL);
RL = AL + CL.
The CAS latency is programmable value. It may be recommended to leave its value without changing,
as in the (Excel) tool suggested. Note, tCL may depend on DDR frequency and the same value must be
used in i.MX6 MMDC and DRAM part (in Mode Register MR0).
From DRAM Datasheet, Table 2 (Speed Grade Information), recommended CL is 11 clocks for 800 MHz
memory device, meaning 13.75 ns; for 400 MHz, 13.75 ns is 6 clocks.
In the (Excel) table, 7 is taken for assurance.
Have a great day,
Yuri
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Yuri
Thank you very much for your feedback.
Then what should be the tCWL value for the Excel table ?
Is that same as tCL ?
Could you please help me on this ?
Regards,
Peter.
Generally it is possible to have different CAS latencies for read and write operations.
Good practice is to leave this parameter as the Excel table recommends.
~Yuri.
Yuri
Thank you. But it is saying obtain this value from ddr data sheet. I cant see tCWL value in data sheet.
Is that okay to leave it as 6 ?
Regards,
Peter.
The memory Datasheet states about 11 clocks for 800 MHz.
Therefore the values of the tool are quire reasonable for specific (400 MHz)
configuration.
~Yuri.