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Current-limit PWM

Question asked by Ivan P on Aug 24, 2018
Latest reply on Aug 24, 2018 by Ivan P


I have MC56F82748VLH chip and I want to generate PWM in complementary mode. The type of PWM (Current-limit PWM) I want to achieve is controlled by varying the duty cycle - when the inductor current reaches a desired maximum value the PWM truncates/turn-off the edge value VAL3. I saw this type of control in the AN4485 application note for the MC56F82xx chip and the correlated example code.

The problem I have is that the reference manuals of the 2 chips is very different and I don't understand how to setup the comparator. The comparator has to generate a fault/trip event which truncates the PWM signal.

1. The PWM fault needs to be enabled, for which I created the following code:

// Set fault disable mapping register




//Disable fault filter

PWMA_FFILT0 = 0x00U;

PWMA_FFILT1 = 0x00U;


// Fault Status Register - Set only full cycle fault clearing timing

PWMA_FSTS0 = 0x0010U;

PWMA_FSTS1 = 0x0010U;


//Set logic 1 as fault level and automatic clearing mode

PWMA_FCTRL0 = 0x0100U;

PWMA_FCTRL1 = 0x0100U;


In the reference manual there are 2 x FFILT(0/1), 2 x FSTS (0/1), 2 x FCTRL (0/1) but for the 0s and 1s the explanation, functions and registers are exactly the same. Does it need that I need only one - either 0 or 1 register and how do you choose which one to use?


2. My chip has a DAC function which can be used either on its own (12-bit) but also has a 6-bit DAC on the comparator. I need to use the 12bit one, but how can I generate the trip/fault signals from the comparator to truncate the PWM? In the example code for the MC56F82xx I believe that it has been used the built-in DAC of the comparator to generate the fault signal. Any ideas how to achieve that with the external DAC synchronized with the comparator?


3. Comparator - which registers needs to be set?




CMPV_DACCR - does it needs to be used this register when using the external 12bit DAC?



Thank you!