AnsweredAssumed Answered

LS2085AQDS USB and SATA issue

Question asked by SAM LAY on Aug 25, 2018
Latest reply on Sep 6, 2018 by SAM LAY

Hi all,

I'm using LS2085AQDS Board + Layerscape2-SDK-SOURCE-20150515-yocto.ISO for development, in this USB 3.0 port and SATA is there, but that is not getting detected when i insert a pendrive and SATA HDD in that.. I checked that in u-boot as well as in kernel. I checked with all the usb  and scsi commands available in u-boot and also checked the dmesg in kernel.. inserted and removed the pendrive continuously but there is no entries in dmesg..,booting information as below, and uboot and rcw,pbl,kernel,MC firmware used the default RCW in the SDK ISO,Would you help me to make it working..

 

U-Boot 2015.01Layerscape2-SDK+g16c10aa (Aug 23 2018 - 18:29:30)

 

SoC:  LS2085E (0x87010010)
Clock Configuration:
       CPU0(A57):1800 MHz  CPU1(A57):1800 MHz  CPU2(A57):1800 MHz  
       CPU3(A57):1800 MHz  CPU4(A57):1800 MHz  CPU5(A57):1800 MHz  
       CPU6(A57):1800 MHz  CPU7(A57):1800 MHz  
       Bus:      600  MHz  DDR:      1866.667 MT/s     DP-DDR:   1600 MT/s
Reset Configuration Word (RCW):
       00: 48303830 48480048 00000000 00000000
       10: 00000000 00200000 00200000 00000000
       20: 00c12980 00002580 00000000 00000000
       30: 00000e0b 00000000 00000000 00000000
       40: 00000000 00000000 00000000 00000000
       50: 00000000 00000000 00000000 00000000
       60: 00000000 00000000 00027000 00000000
       70: 492a0000 00000000 00000000 00000000
Board: LS2085E-QDS, Board Arch: V1, Board version: B, boot from vBank: 0
FPGA: v5 (LS2085AQDS_2015_0218_1606), build 132 on Wed Feb 18 22:06:38 2015
SERDES1 Reference : Clock1 = 156.25MHz Clock2 = 156.25MHz
SERDES2 Reference : Clock1 = 100 separate SSCGMHz Clock2 = 100 separate SSCGMHz
I2C:   ready
DRAM:  Initializing DDR....using SPD
DDR: failed to read SPD from address 81
SPD error on controller 0! Trying fallback to raw timing calculation
Detected UDIMM Fixed DDR on board
Detected UDIMM 18ASF1G72AZ-2G1A1
DP-DDR:  Detected UDIMM 18ASF1G72AZ-2G1A1
19.5 GiB
DDR    15.5 GiB (DDR4, 64-bit, CL=13, ECC on)
       DDR Controller Interleaving Mode: 256B
       DDR Chip-Select Interleaving Mode: CS0+CS1
DP-DDR 4 GiB (DDR4, 32-bit, CL=11, ECC on)
       DDR Chip-Select Interleaving Mode: CS0+CS1
Waking secondary cores to start from fff17000
All (8) cores are up.
Using SERDES1 Protocol: 42 (0x2a)
Using SERDES2 Protocol: 73 (0x49)
Flash: 128 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
EEPROM: NXID v1
PCIe1: disabled
PCIe2: disabled
PCIe3: disabled
PCIe4: Root Complex x1 gen1, regs @ 0x3700000
     01:00.0    - 8086:10d3 - Network controller
PCIe4: Bus 00 - 01
In:    serial
Out:   serial
Err:   serial
Error! Not a FIT image
SATA link 0 timeout.
AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst
Found 0 device(s).
SCSI:  Net:   qds: WRIOP: Supported SerDes Protocol 0x2a
qds: WRIOP: Supported SerDes Protocol 0x49
mdio_register: non unique device name 'FSL_MDIO1'
Phy 28 not found
PHY reset timed out
Phy 29 not found
PHY reset timed out
Phy 30 not found
PHY reset timed out
Phy 31 not found
PHY reset timed out
crc32+
fsl-mc: Booting Management Complex ... SUCCESS
fsl-mc: Management Complex booted (version: 7.0.2, boot status: 0x1)
fsl-mc: Deploying data path layout ... SUCCESS
e1000: 68:05:ca:36:a1:b1
       DPNI1, DPNI2, DPNI3, DPNI4, DPNI5, DPNI6, DPNI7, DPNI8, DPNI9, DPNI10, DPNI11, DPNI12, e1000#0 [PRIME]
Warning: e1000#0 MAC addresses don't match:
Address in SROM is         68:05:ca:36:a1:b1
Address in environment is  00:04:9f:03:ac:08

 

Hit any key to stop autoboot:  0
=> usb start
(Re)start USB...
USB0:   Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
USB1:   Register 200017f NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus 1 for devices... 1 USB Device(s) found
       scanning usb for storage devices... 0 Storage Device(s) found
=> scsi scan
scanning bus for devices...
Found 0 device(s).
=>

Outcomes