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How to run the DDR calibration timing processes as part of the boot sequence each time a device is powered on.

Question asked by Peter Amond on Aug 21, 2018
Latest reply on Aug 22, 2018 by igorpadykov

Dear all,


@Oliver Chen


1) According to following documentation of AN4467.pdf how the user can force the use of DDR timing calibrations (DQS gating, Write leveling and Write/Read DQS delay calibrations) as part of a routine boot sequence using the DDR controller iterative calibration sequence features using NXP stress tester (DDR calibration tools) tool?