I have another question regarding the GPCM mode of the LS1046A IFC.
21.3.7 Chip-Select Option register - GPCM (IFC_CSORn_GPCM)
it says for BURST_LEN:
GPCM burst length. It defines the maximum number of beats that will be sent/received in one burst cycle. This is programmed in terms of port-size transfer. For example, if the port size is 2 bytes and burst_length is 2, then the total of 8 bytes will be transferred in one burst cycle (that is, 4 beats of data transfers and each data transfer of 2 bytes).
Could someone please explain why a burst length of 2 results in 4 beats of data transfer?
Would I get only 2 beats if the port size were 1 Byte?
With the example given I could tranfer either 2 Bytes (no burst) or 8 Bytes (16, 32, ...). Is this somehow related to the internal architecture/bus width?