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IFC: GPCM - minimum timing values / TRHZ

Question asked by Ferdinand Grossmann on Aug 21, 2018
Latest reply on Aug 21, 2018 by Ferdinand Grossmann

Hello everyone,

 

I have some questions regarding the timing parameters programmable in normal GPCM mode of the IFC in the LS1046A.

 

In the reference manual under

21.3.9 Flash Timing register 0 for Chip Select n - NAND flash asyncNVDDR mode (IFC_FTIM0_CSn_NAND)

it says:

...
• For normal GPCM mode (write transaction) all the three
timing parameters (that is, TEAHC, TACSE, and TCS)
should not be programmed zero together.
• For normal GPCM mode (read transaction) all the three
timing parameters (that is, TEAHC, TACSE, and TACO)
should not be programmed zero together.

...

 

But the register descriptions for these values all show 0 as reserved and 1 as the smallest possible value.

What is correct? For example, can I set chip select and output active at the same time?

 

My second question regards the TRHZ turnaround/hold-off time after a read access. According to the manual the minimum time is 20 ip_clks.

Is there any way to turn this off? And will TRHZ always be applied between accesses from the IFC, or only if the accesses are for different chip selects? That is, can back to back read operation be executed faster if they're accessing the same memory device?

20 ip_clks is 100ns in my case (400MHz platform clk) and this delay between accesses would reduce my data throughput drastically...

 

Thanks for any comments!

 

Regards

Ferdinand

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