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How to configure LPC43xx PLL0AUDIO frequency

Question asked by Sam Chen on Aug 21, 2018
Latest reply on Sep 6, 2018 by soledad

Hi all

 

I am using om13088 development board, and try to configure clk0-pll0audio clock to 512fs where fs is 48kHz.

I am follow here to setup pll.

https://www.nxp.com/docs/en/user-guide/UM10503.pdf 

Here is my configuration in board.c

static const CGU_USBAUDIO_PLL_SETUP_T audioPLLSetup = {
0x0000601D, 
0x0 ,

0x0000201d ,
0x16872b, 
24576000\
};

 

Chip_SCU_PinMuxSet (0x6, 0, (SCU_PINIO_FAST | SCU_MODE_FUNC4)); /* I2S0_RX_SCK */
Chip_SCU_PinMuxSet (0x6, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC3)); /* I2S0_RX_WS */
Chip_SCU_PinMuxSet (0x3, 5, (SCU_PINIO_FAST | SCU_MODE_FUNC5)); /* I2S0_TX_SDA */
Chip_SCU_PinMuxSet (0x3, 2, (SCU_PINIO_FAST | SCU_MODE_FUNC1)); /* I2S0_RX_SDA */
Chip_SCU_PinMuxSet (0x3, 1, (SCU_PINIO_FAST | SCU_MODE_FUNC0)); /* I2S0_TX_WS */
/* set clk0 function to CLKOUT and clk0 is connected to PLL0-AUDIO */
Chip_SCU_ClockPinMuxSet(0,(SCU_MODE_FUNC1|SCU_MODE_INACT));
/* Setup base clock for CLKOUT */
Chip_Clock_SetupPLL(CLKIN_IRC, CGU_AUDIO_PLL, &audioPLLSetup);
Chip_Clock_EnablePLL(CGU_AUDIO_PLL);
Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_AUDIOPLL, false, false);

 

The output frequency with above setting is 48Mhz

Dose anyone have ideas about how to set pll0audio?

 

Thanks.

Sam

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