SPI DMA Mode Fails to clock in 3rd to last byte unless CLK speed is reduced

[audreyhendon]

I am doing 8 bit SPI DMA transfers with the KL82Z, and my 3rd to last byte fails to clock in properly. The last two bytes are received and match what I am seeing on the MISO line, but the 3rd to last byte is completely missed, resulting in shifted data. 

I was using an internal reference clock of 4MHz, with a SPI clock of 1MHz.

I dropped the SPI clock down to 500kHz, and the problem was resolved. Does anyone know why this issue was happening at the higher speed? 

[jingpan]

Hi Audrey,

When DSPI is configured with continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60MHz, SPI clock should not be greater than 10MHz.

Regards,

Jing

[JHinkle]

I posted a similar question a couple of days ago.

https://community.nxp.com/thread/482604

I'm clocking at 120mhz  with a SPI baude of 6mhz-- no issue with correct data on the MOIS line except for the third byte from the start not appearing on the output.

We may both have the same issue but different results based on SPI or DMA registers setup.

Here is my DMA and SPI setup - How does it compare to yours?

[CODE]

********************************************

DMA

********************************************

DMA_CERQ = DMA_CERQ_CERQ(13) ; // now disable chan13 for triggers
DMA_TCD13_SOFF = 1; // 1 byte move address offset
DMA_TCD13_ATTR = DMA_ATTR_SMOD(0) | DMA_ATTR_SSIZE(0) | DMA_ATTR_DMOD(0) | DMA_ATTR_DSIZE(0); // no circular addressing S&D, 8 bit S&D
DMA_TCD13_NBYTES_MLNO = 1; // 8bit sample every minor loop
DMA_TCD13_NBYTES_MLOFFNO = 1;
DMA_TCD13_NBYTES_MLOFFYES = 1;
DMA_TCD13_SLAST = 0; // not needed -- IRQ will set new start
DMA_TCD13_DOFF = 0; // no offset - always spi xmit
DMA_TCD13_DLASTSGA = 0; // no final last adjustment ( does not move )
DMA_TCD13_CSR = DMA_CSR_INTMAJOR_MASK ; // interrupt when done
DMA_TCD13_DADDR = (dword)&SPI0_PUSHR;

********************************************

SPI

******************************************

SPI0_SR = 0xffff0000; // clear all pending status flags

SPI0_MCR = SPI_MCR_MSTR_MASK | // master mode
SPI_MCR_DIS_TXF_MASK |
SPI_MCR_CLR_RXF_MASK | SPI_MCR_CLR_TXF_MASK | // // clr both FIFO's .. debug
SPI_MCR_PCSIS(0); //0x0f); //| // identify E1, E2, EE1, EE2 chip selects

My_SPI_RSER = SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK; // xmit avail dma flag

SPI0_CTAR0 = SPI_CTAR_FMSZ(7) | // Data is 8 bits

SPI_CTAR_DBR_MASK | // double clock speed so baud is 12mhz

SPI_CTAR_CPOL_MASK | // Clock Polarity HI at Idle
SPI_CTAR_CPHA_MASK | // Clock Phase - out on leading edge, in on falling
SPI_CTAR_PCSSCK(0) | // delay prescaler - CS and Clock Edge
SPI_CTAR_PASC(0) | // delay prescaler - last clk edge and CS off
SPI_CTAR_PDT(0) | // delay prescaler between CS off and CS on -- between frames
SPI_CTAR_PBR(2) | // Bard Rate .. 2 == divide by 5 ... 60/5 = 12
SPI_CTAR_CSSCK(0) | // actual delay between CS and first clk edge
SPI_CTAR_ASC(0) | // actual delay last clk and CS off
SPI_CTAR_DT(0) | // actual delay between frames
SPI_CTAR_BR(0); // baud rate scaler ... 12 / 2 = 6

DMA_TCD13_SADDR = (dword)Work.Data;

DMA_TCD13_CITER_ELINKNO = NumberOfBytes;
DMA_TCD13_BITER_ELINKNO = NumberOfBytes;

SPI0_MCR |= SPI_MCR_CLR_TXF_MASK; // clear any waiting data

DMA_SERQ = DMA_SERQ_SERQ(13) ; // now enable chan13 for triggers

SPI0_RSER = My_SPI_RSER;

DMA_SSRT = DMA_SSRT_SSRT(13); // start transfer

[/CODE]