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SPI DMA Mode Fails to clock in 3rd to last byte unless CLK speed is reduced

Question asked by Audrey Hendon on Aug 20, 2018
Latest reply on Aug 20, 2018 by Jing Pan

I am doing 8 bit SPI DMA transfers with the KL82Z, and my 3rd to last byte fails to clock in properly. The last two bytes are received and match what I am seeing on the MISO line, but the 3rd to last byte is completely missed, resulting in shifted data. 


I was using an internal reference clock of 4MHz, with a SPI clock of 1MHz.


I dropped the SPI clock down to 500kHz, and the problem was resolved. Does anyone know why this issue was happening at the higher speed?