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Need help about S12 ADC

Question asked by wu wenbin on Aug 17, 2018
Latest reply on Aug 26, 2018 by wu wenbin

Hi

Question1:e6181 workaround:  The ADC  should not be disabled before any flow control request (SEQA,TRIG,RSTA)is finished(all flow control bits are cleared).

so 

 ADC0CTL_0_ADC_SR = 1;//execute ADC soft-reset(SR),ADC enters IDLE state
while(ADC0STS_READY == 0){}
ADC0CTL_0 = 0X00;//ADC is disabled 

or

ADC0CTL_0_ADC_SR = 1;
while(ADC0STS_READY == 0){}

ADC0FLWCTL = 0X80;//need? 

while(0 != ADC0FLWCTL ){}//need?

ADC0CTL_0 = 0X00;//ADC is disabled 

Are both the programs correct?

 

Question2:ATD clock Frequency is 3MHz.10 bit resolution .Then one conversion time ?

if CSL with 17 command entries,then how much time it will cost toally? more details see attachment

thanks!

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