imx8mq sd3.0 fails after tuning

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imx8mq sd3.0 fails after tuning

608 Views
mileswang
Contributor II

Dear Sir,

I want to support imx8mq-evk SD3.0 on VxWork.  I follow the tuning procedure in "sdhci-esdhc-imx.c" as below. But if the tuning is done by calling  esdhc_executing_tuning(), then there is not command response any more. If the tuning is not done, SDR50 works, but SDR104 fails because data CRC error. So I doubt that tuning procedure is not enough. Can you tell me what is missing? Do you have application note to show how to do tuning?  Thanks.

static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
{
u32 reg;

/* FIXME: delay a bit for card to be ready for next tuning due to errors */
mdelay(1);

reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
ESDHC_MIX_CTRL_FBCLK_SEL;
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
dev_dbg(mmc_dev(host->mmc),
"tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
}

static void esdhc_post_tuning(struct sdhci_host *host)
{
u32 reg;

reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
}

static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
{
int min, max, avg, ret;

/* find the mininum delay first which can pass tuning */
min = ESDHC_TUNE_CTRL_MIN;
while (min < ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, min);
if (!mmc_send_tuning(host->mmc, opcode, NULL))
break;
min += ESDHC_TUNE_CTRL_STEP;
}

/* find the maxinum delay which can not pass tuning */
max = min + ESDHC_TUNE_CTRL_STEP;
while (max < ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, max);
if (mmc_send_tuning(host->mmc, opcode, NULL)) {
max -= ESDHC_TUNE_CTRL_STEP;
break;
}
max += ESDHC_TUNE_CTRL_STEP;
}

/* use average delay to get the best timing */
avg = (min + max) / 2;
esdhc_prepare_tuning(host, avg);
ret = mmc_send_tuning(host->mmc, opcode, NULL);
esdhc_post_tuning(host);

dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
ret ? "failed" : "passed", avg, ret);

return ret;
}

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480 Views
igorpadykov
NXP Employee
NXP Employee

Hi Miles

for entering SDR104 mode special voltage switching sequence is needed

performed on i.MX8M EVK by signal SD2_VSELECT, using SD3.0 IO PWR,

NVCC_SD2 U1601 p.19 SPF-29615

Schematics (1)
Design Files for the i.MX 8M Evaluation Kit (EVK)(REV 0)
https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/evaluatio...

Switching and tuning procedure are described in SD3 specification, one can look on

Simplified Specifications - SD Association 

So one can try with Demo Images and i.MX8M EVK and compare behaviour with custom board

https://www.nxp.com/webapp/Download?colCode=L4.9.51_IMX8MQ_GA&appType=license&location=null&Parent_n... 

Best regards
igor
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