I am trying to establish partitioning of the L3 cache to isolate certain cores owing to over usage of the cache by other cores. Looking at the EREF the level 2 cache is controlled by the PIR register but the T4240 reference manual says the L3 is controlled by the PID register. Should this not be the PIR register.
Also, the PIR register does not appear to be setup in accordance with the reference manual. All the thread 1's have correct values in the PIR register but thread 0 is incorrect ie.
core 17 PIR=0x41
core 18 PIR=0x12
core 19 PIR=0x49
core 20 PIR=0x20
core 21 PIR=0x51
Does anyone have code showing how to partition both L2 and L3 cache?