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When is ENDPTCOMPLETE set?

Question asked by Rex Lam on Aug 14, 2018
Latest reply on Aug 16, 2018 by jeremyzhou

I am new to ARM development, and have been looking into an odd behavior in a legacy product which uses LPC1837. The USB0 ISR processes ENDPTCOMPLETE but sometimes it is not set at the end of a USB transaction (or there was no interrupt), e.g. SetConfiguration. In the ISR, USB0 interrupt is disabled like this:

NVIC_DisableIRQ(USB0_IRQn);

 

Then before leaving the ISR, it is reenabled:
NVIC_EnableIRQ(USB0_IRQn);

 

I took USB traces and found no pattern to explain why ENDPTCOMPLETE is sometimes not set. As far as I know, this has only happened during IN transactions. Moving the USB device to a different USB port, or adding an extension USB cable, or adding a hub in between the host and the device could make the problem go away.

 

Could ENDPTCOMPLETE be affected by the disabling of the IRQ? What is the expected behavior of when ENDPTCOMPLETE is set? Is ENDPTCOMPLETE set for each USB transaction or USB transfer? Any guidance would be greatly appreciated.

 

Rex

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