I am developing custom board based on i.MX6 ULL.
I was checking the DDRrouting in the layout files of the MCIMX6ULL-EVK (Allegro board layout files publicly available from NXP website).
I noticed the ADDR13 line has an unusually big length of 1411.4173 mils (measured with Allegro). The average length of the address lines is 1386.5559 mils, and other tracks do not deviate more than 10 mils from this value.
To my understanding, the ADDR13 is violating the design rules of the document IMX6ULHDG "Hardware Development Guide for the i.MX 6UltraLite Applications Processor", page 25, table 22: "Match the signals ± 25 mils."
My question is: This extra length is intentional? In my design, can I make this track shorter and close to the average of the rest of the lanes of this address bus? Or should I make it longer, to overcome an undocumented issue?