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SD/SDIO tuning registers

Question asked by Carsten Hansen on Aug 13, 2018
Latest reply on Sep 5, 2018 by Carsten Hansen

We are having some difficulty with SDIO tuning on an iMX7D design, using a third-party WLAN module connected to the uSDHC1 interface, running in SDR104 mode.


The Linux driver implements standard tuning by default, however this has turned out to cause some instability as we observe occasional CRC errors on received data, typically within a few minutes.


Modifying the driver to use manual tuning instead seems to have solved this issue. However, we are struggling to understand the meaning of some bit groups in the uSDHC block.


From the iMX7D Reference Manual, rev 1, Jan 2018:

  1. p2892, uSDHCx_CLK_TUNE_CTRL_STATUS, the table refers to CLK_PRE, CLK_OUT and CLK_POST. What exactly are these clocks, where do they come from, and where do they go to? They are obviously important, but we can't find any mention of them anywhere else in the RM
  2. p2896, uSDHCx_STROBE_DLL_STATUS, there's mention of a reference delay line as well as a slave delay line. What are those? Figure 10-54 on page 2815 only shows a single delay line
  3. p2904, uSDHCx_TUNING_CTRL, what is the significance of the TUNING_WINDOW bit group? The description has "Select data window value for auto tuning" but we're not sure what that means


We've gone through the SD Specifications including the Host Controller spec, but have been unable to find more information. And in any case this seems to be processor specific, so probably wouldn't be documented there.


Any insights much appreciated.