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MCIMX6Q5EYM10AD

Question asked by zhang han on Aug 11, 2018
Latest reply on Aug 16, 2018 by zhang han

I use MCIMX6Q5EYM10AD in my design , When I continuously restart the device。Sometimes it will be stuck at uboot, and it will not restart until  to power on again. What could cause this problem?

 

 

The information that starts normally is as follows

 

U-Boot 2015.04 (Sep 28 2017 - 10:39:13)

CPU: Freescale i.MX6Q rev1.5 at 792 MHz
CPU: Temperature 43 C
Reset cause: POR
Board: MYZR i.MX6 Evaluation Kit
Model: MY-IMX6-EK314-6Q-1G
I2C: ready
DRAM: 1 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment

No panel detected: default to Hannstar-XGA
Display: Hannstar-XGA (1024x600)
In: serial
Out: serial
Err: serial
Net: using phy at 0
FEC [PRIME]
Normal Boot
Hit any key to stop autoboot: 0
switch to partitions #0, OK
mmc1(part 0) is current device
reading zImage-myimx6
6491336 bytes read in 182 ms (34 MiB/s)
Booting from mmc ...
reading myimx6ek314-6q.dtb
42908 bytes read in 19 ms (2.2 MiB/s)
Kernel image @ 0x12000000 [ 0x000000 - 0x630cc8 ]
## Flattened Device Tree blob at 18000000
Booting using the fdt blob at 0x18000000
Using Device Tree in place at 18000000, end 1800d79b

Starting kernel ...

Booting Linux on physical CPU 0x0
Linux version 3.14.52 (antimax@antimax-imx61) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #42 SMP PREEMPT Tue Jan 30 19:01:41 CST 2018
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: MYZR i.MX6 Evaluation Kit (MY-IMX6-EK314-6Q)
cma: CMA: reserved 320 MiB at 3c000000
Memory policy: Data cache writealloc
PERCPU: Embedded 8 pages/cpu @ab723000 s8448 r8192 d16128 u32768
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 260096
Kernel command line: console=ttymxc0,115200 root=/dev/mmcblk3p2 rootwait rw
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 699052K/1048576K available (7261K kernel code, 528K rwdata, 3328K rodata, 380K init, 424K bss, 349524K reserved, 0K highmem)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xc0800000 - 0xff000000 (1000 MB)
lowmem : 0x80000000 - 0xc0000000 (1024 MB)
pkmap : 0x7fe00000 - 0x80000000 ( 2 MB)
modules : 0x7f000000 - 0x7fe00000 ( 14 MB)
.text : 0x80008000 - 0x80a5f944 (10591 kB)
.init : 0x80a60000 - 0x80abf100 ( 381 kB)
.data : 0x80ac0000 - 0x80b44160 ( 529 kB)
.bss : 0x80b4416c - 0x80bae1d8 ( 425 kB)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Preemptible hierarchical RCU implementation.
NR_IRQS:16 nr_irqs:16 16
L310 cache controller enabled
l2x0: 16 ways, CACHE_ID 0x410000c7, AUX_CTRL 0x32070000, Cache size: 1024 kB
Switching to timer-based delay loop
sched_clock: 32 bits at 3000kHz, resolution 333ns, wraps every 1431655765682ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 6.00 BogoMIPS (lpj=30000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x106ee138 - 0x106ee190
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU2: Booted secondary processor
CPU2: thread -1, cpu 2, socket 0, mpidr 80000002
CPU3: Booted secondary processor
CPU3: thread -1, cpu 3, socket 0, mpidr 80000003
Brought up 4 CPUs
SMP: Total of 4 processors activated (24.00 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
pinctrl core: initialized pinctrl subsystem
regulator-dummy: no parameters
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
CPU identified as i.MX6Q, silicon rev 1.5
Use WDOG1 as reset source
syscon 20c8000.anatop: regmap [mem 0x020c8000-0x020c8fff] registered
vdd1p1: 800 <--> 1375 mV at 1100 mV
vdd3p0: 2625 <--> 3400 mV at 3000 mV
vdd2p5: 2000 <--> 2750 mV at 2400 mV
vddarm: 725 <--> 1450 mV at 1150 mV
vddpu: 725 <--> 1450 mV
vddsoc: 725 <--> 1450 mV at 1175 mV
syscon 20e0000.iomuxc-gpr: regmap [mem 0x020e0000-0x020e0037] registered
syscon 21bc000.ocotp-ctrl: regmap [mem 0x021bc000-0x021bffff] registered
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
imx6q-pinctrl 20e0000.iomuxc: Invalid fsl,pins property in node /soc/aips-bus@02000000/iomuxc@020e0000/myimx6ek314-6qu/rstgrp
imx6q-pinctrl 20e0000.iomuxc: Invalid fsl,pins property in node /soc/aips-bus@02000000/iomuxc@020e0000/myimx6ek314-6qu/hhts_gt9xxgrp
imx6q-pinctrl 20e0000.iomuxc: Invalid fsl,pins property in node /soc/aips-

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