IMX6UL pin getting damaged, either getting short with GND or VCC and GND getting short

[sadatanvashisth]

We are using imx6UL chip MCIMX6G0DVM05AA in our board where in we have configured below pins:

C14-->ecspi1.SCLK

A14-->ecspi1.MOSI

B16-->ecspi1.MISO

D3-->ecspi1.SS0

These pin are being used to communicate with a MCU (STM32F7) on other board . The connectivity is done over a wire harness with length of around mm. We have put series termination resistor on i.e. the SCLK, MISO and MOSI signal  tuned to keep the over shoot in signal level with in acceptable range of voltage i.e. Vdd(3.3V) +0.6V.

But we are observing that these pins are getting damaged very frequently. Even NSS pin which is not switching at very high frequency got damaged some time.

Do we need to put some other protection device on these pins. Our SPI communication is working on 12MHz.

Please find below interface diagram for SPI Bus

[igorpadykov]

Hi sadatan

yes one can consider to add additional protection device on these pins. 

Also recommended to check power up sequence, in particular that no external

voltages should be applied to unpowered i.mx device.

Best regards
igor
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[sadatanvashisth]

when you are saying that no external power should be connected to unpowered device then what should be done in case USB is connected and VBUS is going to MPU but system is either fully -off or in sleep mode.

[igorpadykov]

usb are exception please refer to

[sadatanvashisth]

Hi Igor,

Thanks for the reply.

Please see my query below regarding the damage of a particular pin with the details of pin configuration and let me know your comments:

   SPI clock configuration: Pol (1), phase (1)

•      NSS pin configuration: 0x13088h
•      NSS pin: As an Output
•      NSS ball Number: D3
•      No series resistance on NSS pin connection (Master to Slave)
•      Overshoot: 16% of VDD
•      Power consumption on pin: 5mA max (as per equation Imax = N*V*C*0.5*F)

Questions:

1.      What is the state of NSS pin after resting processor? (Note: Driver is unloaded after reset)
2.     What is the state of NSS pin while booting the processor as it is configured as keeper? (Note: Driver is still not loaded)
3.     What are the chances of NSS pin getting damaged when accidently removed while system is running?
4.     Can series resistance serve the purpose?

Regards,

Sadatan

[sadatanvashisth]

Any comments on this?

[igorpadykov]

Hi Sadatan

for overshoot requirements one can look at i.MX6UL Datasheet
http://www.nxp.com/docs/en/data-sheet/IMX6ULCEC.pdf

ESD is described in Hardware Development Guide for the i.MX 6UltraLite Applications Processor (sect.3.9 ESD..)
https://www.nxp.com/docs/en/user-guide/IMX6ULHDG.pdf

Best regards
igor

[sadatanvashisth]

Thanks for the reply igor.

But can you please provide your input on blow queries as well:

1.      What is the state of NSS pin after resting processor? (Note: Driver is unloaded after reset)
2.     What is the state of NSS pin while booting the processor as it is configured as keeper? (Note: Driver is still not loaded)
3.     What are the chances of NSS pin getting damaged when accidently removed while system is running?
4.     Can series resistance serve the purpose?

[igorpadykov]

Hi Sadatan

reset state is given in Table 91. 14x14 mm Functional Contact Assignments

ESD Immunity in Table 8. Absolute Maximum Ratings i.MX6UL Datasheet
http://www.nxp.com/docs/en/data-sheet/IMX6ULCEC.pdf

Best regards
igor

[sadatanvashisth]

Thanks for reply igor.

But I want to know when I am using nss pin in SPI mode and if is getting reset then it says  it will be input Keeper, so what will be the signal level of that pin?

[igorpadykov]

please check keeper description

Bus-holder - Wikipedia 

So generally, it may have any level.

Best regards
igor

[sadatanvashisth]

Thanks for your inputs igor. Can you please suggest what type of protection we can plan on these pins. Our IO voltage is 3.3V.

[igorpadykov]

one can try for example ESD7C used as usb protection

on i.MX6UL EVK p.6 schematic.

Best regards
igor