We are using an SGTL5000 in slave mode, outputting data to a processor via I2S.
Due to processor limitations on the ratios between the three clocks, we have values of MCLK, SCLK and LRCLK of 8192, 1024 and 32 kHz, respectively. This all works as expected, which is great.
However, we only actually need LRCLK to be 8 kHz, but the only way that we can do that (due to the aforementioned processor constraints) would be to reduce the rate of all three clocks by a factor of 4. This would reduce the master clock to 2048 kHz, which appears to be below the minimum mentioned in the datasheet.
Given that doing this is out of spec, should we avoid it?
I get the impression that if we switched to master mode and used the internal PLL, we may be able to get around this problem, so that may be the back-up plan if reducing the master clock is not allowed.