MKW41Z internal DCDC configuration on a customized PCB

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MKW41Z internal DCDC configuration on a customized PCB

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gerardocatena
Contributor II

Hi,

I want to share what we have experienced during the development of our customized PCB to see if we did some error due to a missed technical reading or if what we have experienced is a common practice.

After a while playing around the FRDMKW41Z we produced our custom PCB with the MKW41Z MCU.

We configured the hardware in buck mode manual start. We used the documentation related to the FRDM board as a driver in implementing our custom schematic and gerber. Finally we used with success the FRDMKW41Z to program the custom board bypassing the resident MCU. When we debug the firmware the custom PCB is about 3.6V powered and the FRDM board is connected to the laptop USB.

Below the details of hardware and firmware config related to the DCDC:

THE HARDWARE CONFIGURATION:

- VDD_1P8 and VDD_IP5 inductor -> 0.1uH

- VDD_1P8 and VDD_1P5 capacitors -> 10uF.

- DCDC Inductor -> 10uH.

THE FIRMWARE CONFIGURATION:

The firmware starts to VDD_1P8 at 1.8V. After it is configured to work at 3V because one of our external peripherals needs of 3V signals to communicate.

Here is an excerpt of the code in board.c used to switch from 1.8V to 3V on 1P8.

....

BOARD_BootClockRUN();

BOARD_DCDCInit();

while((DCDC->REG0 & DCDC_REG0_DCDC_STS_DC_OK_MASK)==0){}
DCDC->REG3 = (((DCDC->REG3) & (~DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK)) | DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP(0));
DCDC->REG3 = (((DCDC->REG3) & (~DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK)) | DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(0));
DCDC_SetOutputVoltageTargets(gDCDC_McuV_OutputTargetVal_1_500_c, gDCDC_1P8OutputTargetVal_3_025_c);
while((DCDC->REG0 & DCDC_REG0_DCDC_STS_DC_OK_MASK)==0){}

....

THE FIRMWARE BEHAVIOR:
The firmware, after the startup of the main_task and some custom module, calls PWR_ChangeDeepSleepMode(2) and puts the MCU in power down (LLS2 mode). In this state the MCU is sleeping, waiting for a wake-up signal from a key.
We checked that it correctly enters in power down through the oscilloscope: the DCDC enters in pulse mode.
On exit from power down we experienced two results:


1- If the VDD and GND signals of our custom PCB are plugged to the programmer (the FRDMKW41Z) it exits from power down after a key pressure and the waveform of the DCDC changes in continuous mode. This happens even if the FRDM isn't plugged to the USB. If a debug session in opened after a key pressure the debugger comes available again.

2- if we disconnect the above signals of our custom PCB from the FRDMKW41Z, after a key pressure the MCU resets with reset reason 504. The reset on the oscilloscope is evident because it restarts the pulse mode and do not setup the continuous mode. The debug session in unusable.

We seen the pulsed signal having different form of the ripple compared to the form when connected to the FRDMKW41Z.

OUR INVESTIGATION:

As first step we measured the load and the capacitance introduced by the board (which obviously is powered even if it is disconnected from the USB, because connected to VDD and GND of the custom PCB that in turn is 3.6V powered). The results of the measurements are that the FRDM board introduces about 37KOhm of load and about 5uF of cap.

We then introduced 1KOhm load between VDD and GND of the custom PCB and we start to run the firmware without plugging the FRDM board and as results it starts to work normally again, entering and exiting from the pulse mode as if it were plugged to the FRDM board.

In conclusion we have supposed that the load introduced by our custom hardware is too few to make the DCDC working properly. From here we removed the 1KOhm resistor and started to tune the inductor connected to VDD_1P8 until we found an inductor size of 0.47uH which makes our PCB to work as expected.

My questions are: is there a way to left the inductor size to 0.1uH and tune some DCDC register accordingly with our PCB expected load, or is there some technical documentation which helps to compute the expected inductor size? Did we make any mistake?

Regards,

G.

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estephania_mart
NXP TechSupport
NXP TechSupport

Hello, 

By any chance, have you checked the Hardware Design Considerations for MKW41Z/31Z/21Z   under chapter 6.6.2. DCDC inductor. 

Regards, 

Estephania 

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gerardocatena
Contributor II

Hello,

Thank you for the answer.

In my previous mail I was talking about the 0.1uH inductor connected to VDD_1P8OUT pin (labeled L5 into the FRDM schematic) not about the 10uH inductor (labeled L3 into FRDM schematic). However we missed the vias. Could missing vias on L3  produce the reset behavior which in turn is corrected modifying the size of L5?

If yes, how could that reset the MCU when exit from low power? The resets are systematic not random. I expect that the PCB exhibits poor performance in general, even if it is up and running. Probably is happening something related on how the DCDC works internally.

Otherwise If the vias cannot produce what above described, from our hardware tests, the L5 value seems to be related to the minimum load that a given customized PCB introduces when goes in power down mode. This is why I'm asking if this behavior can be due to a wrong pulse mode configuration (we are using connectivity framework default DCDC configuration), or if the right way to face this problem is to tune the size of this inductor on every new PCB.

Regards,

G.

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