I have questions about DDR calibration resistance in Output Driver Average Impedance for i.MX53.
As it mentioned in following thread, the Table 43-2 and 43.3.454 unmatched and we have same question.
But there didn't answer the thread.
Table 43-2 does not describe the DSE value when it set DDR3 dde_sel = 01.
Refer to 43.3.454 IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE and it is explained as "NVCC_EMI_DRAM = 1.5 V +/- 5% (DDR 3), ddr_sel = '' 01: 160 Ohm '
In the case of dde_sel = 01 setting of DDR3, is the value of DSE the same as DDR_SEL = 01/11 of LPDDR 2 mode in Table 43-2 ?
If Q1 is not same, could you provide a DSE value when it set DDR3 dde_sel = 01 ?
We think that the calibration resistance which is shows in yellow line is wrong.
Because there are no settings in Table 43.3.454.
The correct calibration resistance is 200 Ohm. Am I correct ?