Probe point to measure a timing of uSDHC

[takayuki_ishii]

Hello community,

About Figure 40 and Table 51 in Datasheet of IMX6DQPAEC rev2,

Which point does it measured from/to?

In Figure 40, it seems that

SD2: uSDHC Output Delay     from "50% of SD_CLK" to "Voh max value".

SD3: uSDHC Input Setup Time   from "Voh max value" to "50% SD_CLK"

SD4: uSDHC Input Hold Time   from "50% SD_CLK" to "Vol mix value"

Or from "50% SD_CLK" to "50% SD_DATA"?

Which is a correct answer?

Best regards,

Ishii.

[Yuri]

Hello,

SD2 is Output Delay from "50% of SD_CLK" to "Voh min value".

SD3 is Input Setup Time  from "Vih min value" to "50% SD_CLK".

SD4 is Input Hold Time  from "50% SD_CLK" to "Vih min value".

Have a great day,

Yuri

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[takayuki_ishii]

Hello Yuri,

Thank you for your quick response.

How about DDR mode in eMMC?

Figure you attached is a single mode one.

Is it same in DDR mode of eMMC?

We hope to know it because timing is very critical for DDR access.

Best regards,

Ishii.

[Yuri · Accepted solution]

Hello, Ishii!

For DDR mode:

 CLK timing is measured at 50% of VDD.

Inputs CMD, DAT rise and fall times are measured by min (VIH) and max (VIL),

and outputs CMD, DAT rise and fall times are measured by min (VOH) and max (VOL).

Regards,

Yuri.

[takayuki_ishii]

Hello Yuri,

Thank you for your answered.

I will answer it to my customer.

Best regards,

Ishii.