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Are Kinetis MCU's clocks gated

Question asked by MARK BRINKMAN on Jul 31, 2018
Latest reply on Aug 1, 2018 by MARK BRINKMAN

K26FN2M0VMD reference manual 'clocking diagram' shows clock gates on outputs of core, bus, flexbus/SDRAMC and flash clocks. Where are they in the memory map? SIM_SCGC6[0] is the flash clock gate enable bit. What about SIM_SCGC7 bits [3] and [0]? Per the diagram FlexBus and SDRAMC share the same clock gate. What about core and bus clock gates? Reference manual section 7.3.4 item 2 adds to the confusion by stating core, system and flash do not have clock gate controls. Please clarify.

 

thanks

Dino

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