I am currently designing a PCB containing multiple Displayport/HDMI muxes. I want to achieve at least achieve HBR2 (5.4Gbit/s/lane), better even HBR3 (8.1Gbit/s/lane).
Here a signal overview from Wiki:
|DisplayPort pins||DVI/HDMI mode|
|Main Link Lane 0||TMDS Channel 2|
|Main Link Lane 1||TMDS Channel 1|
|Main Link Lane 2||TMDS Channel 0|
|Main Link Lane 3||TMDS Clock|
|AUX CH+||DDC Clock|
|AUX CH−||DDC Data|
|Hot Plug Detect||Hot Plug Detect|
|Config 1||Cable Adaptor Detect|
CEC (HDMI only)
During layout I have considered "AN10798".
It says: "Trace length greatly affects the loss and jitter budgets of the interconnection. The PCB trace may introduce 1 ps to 5 ps of jitter and 0.35 dB to 0.50 dB of loss per inch."
For 1ps and 300.000.000m/s speed (I know it is a bit slower on PCB) it equals to roughly 0,3mm. With 200.000.000m/s and 5ps it still means 1mm. That is fine for the 4 main lanes but aux channel makes it a bit harder in my application.
Now I am wondering, if length matching is only important between the four lanes of main link so aux channel can be of another length (which would give me great freedom in layout) or if the aux pair needs to be within same 0.3~1mm length matching as stated in AN10798.
Just to be clear, I know, that p and n signal needs to be same length, but does the diff pair need to be the same length as the four main link diff pairs?
Thank you very much for your help!