I have been reading through the MPC5746R reference manual but I couldn't get the following information.
Assuming two cores (core-0 and core-1+2 in LS) running in decoupled parallel mode,
How are the peripherals mapped to the two cores? If there is data on one of the IO pins, can both the cores access this data simultaneously? Or are the peripheral pins configured to one core??
Rephrasing the question -> How does the peripheral access work (SIUL2) for the MPC5746R ??
Intention: From safety perspective I would like to understand how sensors are accessed from the two cores.