shi dongxing

MPC 5744P Mode transition fails after modifying PLL0 config

Discussion created by shi dongxing on Jul 23, 2018

Hi NXP Team:

I try to modify PLL0DV configs to modify the system clock frequency.

But the mode transition won't success when I disabled PLL0.

As far as I know, it is necessary to Turn Off and then Turn On the PLL0 to make the changes come into effective.

But the following code will not work:

 

// Enable XOSC, PLL0, PLL1 and enter RUN0 with PLL0 as sys clk (200 MHz)
void SysClk_Init(void)
{
MC_CGM.AC3_SC.B.SELCTL = 0x01; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01; //connect XOSC to the PLL1 input

// Set PLL0 to 200 MHz with 40MHz XOSC reference
PLLDIG.PLL0DV.R = 0x50024028; // PREDIV = 4, MFD = 40, RFDPHI = 2, RFDPHI1 = 10

MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

// Set PLL1 to 320 MHz with 40MHz XOSC reference // todo: need checking
// 0719: not used,ignore
PLLDIG.PLL1DV.R = 0x00010010; // MFD = 16, RFDPHI = 1

MC_ME.RUN_PC[0].R = 0x000000FE; // enable peripherals run in all modes
MC_ME.RUN0_MC.R = 0x001300F2; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL0

MC_CGM.SC_DC0.R = 0x80030000; // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

// MC_CGM.SC_DC0.R = 0x80030000; // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)
MC_CGM.AC0_SC.R = 0x02000000; // Select PLL0 for auxiliary clock 0
MC_CGM.AC0_DC0.R = 0x80030000; // MOTC_CLK : Enable aux clk 0 div by 4 … (50 MHz)
MC_CGM.AC0_DC1.R = 0x80090000; // SGEN_CLK : Enable aux clk 0 div by 10 … (20 MHz)
MC_CGM.AC0_DC2.R = 0x80030000; // ADC_CLK : Enable aux clk 0 div by 4 … (50 MHz)
MC_CGM.AC6_SC.R = 0x04000000; // Select PLL1 for auxiliary clock 6
MC_CGM.AC6_DC0.R = 0x80000000; // CLKOUT0 : Enable aux clk 6 div by 1 … (320 MHz) // todo: Need checking // 0719: not used
MC_CGM.AC10_SC.R = 0x03000000; // Select PLL0 PHI1 for auxiliary clock 10
MC_CGM.AC10_DC0.R = 0x80000000; // ENET_CLK : Enable aux clk 10 div by 1 … (40 MHz)
MC_CGM.AC11_SC.R = 0x03000000; // Select PLL0 PHI1 for auxiliary clock 11
MC_CGM.AC11_DC0.R = 0x80000000; // ENET_TIME_CLK : Enable aux clk 11 div by 1 … (40 MHz)
MC_CGM.AC5_SC.R = 0x01000000; // Select XOSC for auxiliary clock 5
MC_CGM.AC5_DC0.R = 0x80000000; // LFAST_CLK : Enable aux clk 5 div by 1 … (40 MHz)
MC_CGM.AC2_DC0.R = 0x80030000; // CAN_PLL_CLK : Enable aux clk 2 (PLL0) div by 4 … (50 MHz)
MC_CGM.AC1_DC0.R = 0x80030000; // FRAY_PLL_CLK : Enable aux clk 1 (PLL0) div by 4 … (50 MHz)
MC_CGM.AC1_DC1.R = 0x80030000; // SENT_CLK : Enable aux clk 1 (PLL0) div by 4 … (50 MHz)
}

void clk_switch_IRC(void)
{
// do not change RUN0 cfg, just switch PLL0 Source
MC_CGM.AC3_SC.B.SELCTL = 0; //connect IRC to the PLL0 input

// How to change PLL?
PLLDIG.PLL0DV.B.MFD=100;

MC_ME.RUN0_MC.R = 0x001300F2; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL0

MC_CGM.SC_DC0.R = 0x80030000; // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode
}

 

int main()

{

SysClk_Init();

clk_switch_IRC();

}

 

Thanks!

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