We have a custom iMX8mq board we are doing bring up on. Clocks and reset are very similar to the EVK, but we have deviated on some other hardware:
- 1Gb DDR4 (EVK has 3GB LPDDR4)
- Serial terminal on USART4 (EVK on USART1)
- PMIC/power supply configuration is different, but meets datasheet requirements
- Many different peripherals on SPI and I2C
First thing we did was run the DDR calibration and stress test. It passed >30 iterations of the stress test, and I have left it running over this weekend. The code generated was integrated with u-boot to do DDR training at boot time. Our board is using a Yocto Linux based off the official Linux L4.9.51 for i.MX 8MQuad GA release.
Here is the behavior:
I load U-boot and Linux using the NXP mfgtool. From the time the Linux kernel starts booting, 15 seconds later, the system freezes. I am able to log into the shell using the serial terminal prior to the freezing, but I only have about 4 seconds to do anything it freezes. The system seems to be completely unresponsive after this. I connected with JTAG to see what the processor is doing, and the PC is somewhere in the 0x0090_0000-0x0091_FFFF range which is on chip SRAM in the physical memory map. I am able to step the processor and when disassembled it looks like real code, but I'm not sure what it's doing. This is even more odd that this memory range is not in any valid virtual memory region that Linux sets up. I have no idea what code might be running in OCRAM, does Linux put something in there (interrupt/exception vectors or something)?
I have a couple theories. First, I think somehow the change from 3Gb to 1Gb of memory is causing Linux to go off and try to use memory that isn't there resulting in some kind of hard CPU exception. I have attempted to modify u-boot and the device tree to reflect 1Gb of memory, but not sure if I have done all that is needed.
Second, I based the devicetree for our custom board on the EVK device tree. However, it's possible that I either stripped out something essential, or
Finally, it might be possible that there is some additional changes we need to make to support DDR4 memory as opposed to LPDDR4.
I have spent 2 days trying different things and trying to learn something about what is going on. I've run out of ideas at this point, so any help would be appreciated.