Hello.
We have purchased t1040d4rdb board for evaluation of using t1040 in our new product. We need t1040 to support a lof of simultaneously connected pcie devices, total address space of all pcie devices is up to 16GB.
t1040d4rdb initially support 4 pcie controllers and 256GB of address space mapped for each of them.
I suppose (Please say if I wrong) that to change address space, we need to
1. change linux device-tree in file: ./arch/powerpc/boot/dts/fsl/t104xd4rdb.dtsi
2. change u-boot mapping in file ./include/configs/T104XRDB.h
I tried to disable 3 pcie controllers, and map wider address space for 1-st pcie controller, up to 1GB and it seems to work ok, but how to map PCIe address wider, up to 4GB or even 16GB?
Macros SET_TLB_ENTRY, which use constants from T104XRDB.h (CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS) in file tlb.c event not accept 64-bit CONFIG_SYS_PCIE1_MEM_VIRT.
Can anybody help me to map 16GB for PCIe?
Thanks in advance.
Solved! Go to Solution.
Hello Alexander Bobrov,
In u-boot, 1G TLB entry is allocate for PCIe memory space in board/freescale/t104xrdb/tlb.c.
LAWs for PCIe is allocated in drivers/pci/fsl_pci_init.c as the following.
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
Please refer to the following SET_STD_PCIE_INFO definition in arch/powerpc/include/asm/fsl_pci.h.
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}
These PCIe related parameters are defined in include/configs/T104xRDB.h.
u-boot is 32bit, 4G memory space, it is impossible to allocate a large TLB entry for PCIE in u-boot, however Linux Kernel will reallocate TLB entry for PCIe according to the information in dts file.
So, you could allocate large LAW memory space in u-boot according to your requirement to modify PCIe related parameters in include/configs/T104xRDB.h.
Then modify "ranges" in pcix device node to allocate your required size PCIe memory space.
pci0: pcie@ffe240000 {
reg = <0xf 0xfe240000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000
0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
Have a great day,
TIC
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Hello Alexander Bobrov,
In u-boot, 1G TLB entry is allocate for PCIe memory space in board/freescale/t104xrdb/tlb.c.
LAWs for PCIe is allocated in drivers/pci/fsl_pci_init.c as the following.
set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
Please refer to the following SET_STD_PCIE_INFO definition in arch/powerpc/include/asm/fsl_pci.h.
#define SET_STD_PCIE_INFO(x, num) \
{ \
x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}
These PCIe related parameters are defined in include/configs/T104xRDB.h.
u-boot is 32bit, 4G memory space, it is impossible to allocate a large TLB entry for PCIE in u-boot, however Linux Kernel will reallocate TLB entry for PCIe according to the information in dts file.
So, you could allocate large LAW memory space in u-boot according to your requirement to modify PCIe related parameters in include/configs/T104xRDB.h.
Then modify "ranges" in pcix device node to allocate your required size PCIe memory space.
pci0: pcie@ffe240000 {
reg = <0xf 0xfe240000 0 0x10000>;
ranges = <0x02000000 0 0xe0000000 0xc 0x0 0x0 0x10000000
0x01000000 0 0x0 0xf 0xf8000000 0x0 0x00010000>;
pcie@0 {
ranges = <0x02000000 0 0xe0000000
0x02000000 0 0xe0000000
0 0x10000000
0x01000000 0 0x00000000
0x01000000 0 0x00000000
0 0x00010000>;
};
};
Have a great day,
TIC
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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