IMX6UL MPU 8080 LCD shows the RGB pattern on one quarter of the display, and then it is replicated in the others 3 quarter

[kdaadfdafd]

IMX6UL MPU 8080 LCD shows the RGB pattern on one quarter of the display, and then it is replicated in the others 3 quarter. Just like the picture below.    Have any friends encountered this kind of problem ，how to solve it?  Waiting for your help ,thanks very much!

ps:Modified according to the patch:Patch to support MPU 8080 LCD on iMX6UL and iMX7D

[igorpadykov]

Hi kda

please verify initialization sequence for used lcd in its datasheet, as

it is different for different lcds. If that will not help suggest to post question

on 8080 patch link.

Best regards
igor
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[kdaadfdafd]

Thanks for your answer

I have tested it on DSP environment, it should not be an initialization issue. I see some friends, under the link, encountered the same problem. One of the friends mentioned this solution:
"The right configuration was the last, with 18 bpp and 16 bit bus width, but to apply the patch correctly we had to download the L3.14.52_1.1.0_GA NXP Kernel.
 
We applied the patch to the old kernel then, we pastel copied the patched files, to the right paths, to the folder of the fsl-yocto-L4.1.15_2.0.0-ga after menuconfig command via bitbake”

My linux version is linux-imx-4.1.15-r0.  I download the L3.14.52_1.1.0_GA kernel ,use the "git apply" command to get the corresponding files and copy it to my kernel, the Error still...

[igorpadykov]

if you have issues with porting, nxp has special service for helping with that:

NXP Professional Services|NXP 

Best regards
igor

[kdaadfdafd]

3Q,  :smileygrin:

[lvmh]

Hi,kda adfdafd

   I have the same problem as you. Can you give me some advice?

Thanks.

[oguzhandalgic]

Hi Ivmh,

I had the exact same problem and solved it. I realized that it is related to the x and y resolutions of the TFT, i.e. they were entered in reverse order. Check the driver code of the TFT Panel controller.