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i.mx6ull evk dram data 7 and data 2 swapped

Question asked by David Luberger on Jul 12, 2018
Latest reply on Jul 13, 2018 by gusarambula

I'm really confused about a discrepancy I'm seeing between the eval board schematic and layout.  Per the DDR3L datasheet and the i.mx6ULL datasheet, the DDR Data07 should connect from pad U4 on the i.mx6ull to pad H7 on the 96-pin memory (which seems to be a standard DDR pinout).  Likewise, DDR Data02 should connect frmo pad T6 on the i.mx6ull to pad F2 on the DDR3L IC.

 

Here's what's strange.  The datasheets agree with that, the EVK schematic agrees with that BUT the actual layout of the EVK CM module (i.e. the module that has the processor and DRAM) has them swapped, and when I inspect the physical board, what is manufactured follows the layout, and yet everything works.  how can this be??

 

I'm in the middle of laying out my own board, and this discrepancy has me really confused and it's holding things up.  Can someone clarify why and how this works?  The i.mx6ull datasheet clearly shows that the DRAM pads are no-mux. Since the actual eval board works that tells me that not does the datasheet have to be wrong, the schematic has to be wrong too and somehow the designer(s) deviated from the schematic.

 

I'm in a really pinch here. Someone please help!!

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