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DMA bus error accessing SPI pushr

Question asked by Minghao Dai on Jul 12, 2018

I'm trying to have DMA taking charge of SPI TX/RX, I can successfully use DMA to do a RAM to RAM transferring but failed as long as source or destination address is address for register.

 

For DSPI configuration, I have TFFF_RE and TFFF_DIRS set as 1, clocking running at 1MHz.

Supposely as long as TFFF flag is raised, DMA should do transferring.

 

Following is my configuration for DMA setup.

 

void dma_test(void)
{
static uint32_t DSPI_Master_Transmit_Data[8] = {0x80080011U, 0x80080022U, 0x80080033U, 0x80080044U, 0x80080055U, 0x80080066U, 0x80080077U, 0x08080088U};

 

 

DMAMUX.CHCONFIG[0].B.ENBL = 0;
DMAMUX.CHCONFIG[0].B.TRIG = 0;

 

EDMA.DMAERQL.B.ERQ0 = 1U; //channel
//source
EDMA.CHANNEL[0].TCDWORD0_.B.SADDR = (vuint32_t) &DSPI_Master_Transmit_Data[0];
EDMA.CHANNEL[0].TCDWORD4_.B.SSIZE = SIZE_4_BYTE;
EDMA.CHANNEL[0].TCDWORD4_.B.SOFF = 4U; //source has word wide port
EDMA.CHANNEL[0].TCDWORD4_.B.SMOD = 0U; //source modulo feature not used
EDMA.CHANNEL[0].TCDWORD12_.B.SLAST = 0U; //-32;
//destination
EDMA.CHANNEL[0].TCDWORD16_.B.DADDR = (vuint32_t) &DSPI[0]->PUSHR.R;
EDMA.CHANNEL[0].TCDWORD4_.B.DSIZE = SIZE_4_BYTE;
EDMA.CHANNEL[0].TCDWORD4_.B.DMOD = 0U; //destination modulo feature not used
EDMA.CHANNEL[0].TCDWORD20_.B.DOFF = 0U;//4U;// //no increment after tx.
EDMA.CHANNEL[0].TCDWORD24_.B.DLAST_SGA = 0U; // //after major loop, do not change address
//counts
EDMA.CHANNEL[0].TCDWORD8_.B.NBYTES = 4; //4 bytes per minor loop
EDMA.CHANNEL[0].TCDWORD20_.B.CITER = 8U;
EDMA.CHANNEL[0].TCDWORD20_.B.CITER_E_LINK = 0U;
EDMA.CHANNEL[0].TCDWORD20_.B.CITER_LINKCH = 0U;
EDMA.CHANNEL[0].TCDWORD28_.B.BITER = 8U;
EDMA.CHANNEL[0].TCDWORD28_.B.BITER_E_LINK = 0U;
EDMA.CHANNEL[0].TCDWORD28_.B.INT_MAJ = 1U;
EDMA.CHANNEL[0].TCDWORD28_.B.ACTIVE = 0U;
EDMA.CHANNEL[0].TCDWORD28_.B.DONE = 0U;
EDMA.CHANNEL[0].TCDWORD28_.B.START = 0U;


EDMA.DMAINTL.B.INT0 = 1U;

 

DMAMUX.CHCONFIG[0].B.SOURCE = 1U; //DSPI_TFFF
DMAMUX.CHCONFIG[0].B.ENBL = 1U;
}

 

The problem here is when I have either SADDR or DADDR set as the address of register, a bus error (DMAES.SBE/DMAES.DBS) is set in DMA error register. Do I have an incorrect EDMA config? Or there's some memory access limitation? 

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