How to set SPLL clock to 80MHz?

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How to set SPLL clock to 80MHz?

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kbj
Contributor IV

Hi,

I would like to use FS32K144HFT0xxxx MCU.

The MCU's core frequency is 80MHz.

So I try to set SPLL clock to 80MHz with SKD_S32K14x_09 in S32 design studio for ARM.2018.R1

But I could not set SPLL clock to 80MHz, because of below warning.

Is it possible to set SPLL clock to 80MHz?

If it is possible, how to set 80MHz?

2.PNG1.PNG 

Thanks and best regards,

Byungju.

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jiri_kral
NXP Employee
NXP Employee

Hi, 

based on this AN - https://www.nxp.com/docs/en/application-note/AN5408.pdf  the supported range for SPLL is 90-160 MHz. 

Jiri

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kbj
Contributor IV

Dear Jiri,

As your comment, SPLL frequency spec is below.

In case of FS32K144HFT0xxxx MCU, Core frequency is 80MHz.

If I set the SPLL clock of FS32K144HFT0xxxx to 90MHz, Is there any problem in operation?

1.PNG

Best regards,

Byungju.

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jiri_kral
NXP Employee
NXP Employee

Hi, 

the 90MHz is in range  So I'm not expecting any issues. 

Jiri

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kbj
Contributor IV

Dear Jiri,

Thanks for your help.

I have one more question.

I think that the means that core frequency is 80MHz means the configurable max frequency is 80MHz.

Do I misunderstand?

Best regards,

Byungju.

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jiri_kral
NXP Employee
NXP Employee

Hi Byungiju, 

The core clock depends on Run mode. In HSRUN - the core clock should be 112MHz, in normal RUN 80MHz and so on. Please look at chapter 27-30 in reference manual - page 533+ https://www.nxp.com/docs/en/reference-manual/S32K-RM.pdf 

Jiri

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kbj
Contributor IV

Dear Jiri

There are F32K144UAT0VLLT MCU that core frequency is 112MHz and F32K144HRT0VLLT that core frequency is 80MHz.

Both of MCUs can set the SPLL to 90MHz?

If Core frequency is not SPLL requency, What is core frequency?

1.PNG

2.PNG

Thanks and best regards,

Byungju.

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jiri_kral
NXP Employee
NXP Employee

Hi, 

I didn't find any SPLL limitations info for HRT0VLLT variant. So - let's summarize it:

The SPLL clock source is frequency of Oscilator - for example 8MHz. SPLL output range is 90-160MHz -taken from FOSC by dividers/multipliers. 

SPLL output is source for Core clock. You need to use dividers/multipliers in way to satisfy the max allowed core clock for HSRUN. That is how I understand it.

Jiri

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kbj
Contributor IV

Dear Jiri,

Thanks for your reply.


I will repeat the following questions for clarification.
1. What does the Core Frequency in the EXCEL table below mean?

2.PNG


2. If the core frequency is the frequency of normal RUN mode, how do you set it to 80MHz? (If you set it to FIRC, it is max. 60Mhz.)

1.PNG

Best regards,

Byungju.

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jiri_kral
NXP Employee
NXP Employee

Hi, 

The 80MHz in the table means that ARM core can run on 80MHz or less. 

can you share your project? I'm not able set for example FIRC to 60MHz on my project. To check final values is better look at the Clock values summary page:

pastedImage_1.png

Jiri

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kbj
Contributor IV

Dear Jiri,

Thanks for your help.

As you do, I set SYS_CLK of RUN mode to 80MHz.

1.PNG

Best regards,

Byungju.

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