We have a Vybrid-based SoM that we are replacing with an i.MX6ULL SoM. The carrier board which we would like to re-use has an ethernet PHY on it. This phy, (rmii KSZ8081RNB) is using a crystal as clock input and providing ref_clk to the CPU. This was working in the Vybrid case. In the i.MX6ULL case, we attached the phy's REF_CLK to ENET2_TX_CLK, and configured GPR1 for input clock, but it's not working. The reference manual says that ENET2_TX_CLK is only valid in mii mode. Is that the case? Is it not possible for an rmii phy to provide reference clock to the i.MX6ULL at all?