i.MX6ULL ethernet rmii PHY with crystal

[aaronbrice]

We have a Vybrid-based SoM that we are replacing with an i.MX6ULL SoM.  The carrier board which we would like to re-use has an ethernet PHY on it.  This phy, (rmii KSZ8081RNB) is using a crystal as clock input and providing ref_clk to the CPU.  This was working in the Vybrid case.  In the i.MX6ULL case, we attached the phy's REF_CLK to ENET2_TX_CLK, and configured GPR1 for input clock, but it's not working.  The reference manual says that ENET2_TX_CLK is only valid in mii mode.  Is that the case?  Is it not possible for an rmii phy to provide reference clock to the i.MX6ULL at all?

Thanks,

Aaron

[sharadsathvik]

Yes !!!!

it is possible for an rmii phy to provide reference clock to the i.MX6ULL.

Clock direction can be set with GPR1 in arch/arm/mach-imx/mach-imx6ul.c
function imx6ul_enet_clk_init() ,IMX6UL_GPR1_ENET2_CLK_DIR=0 and

ENET2_CLK_SEL=1

Verify in the KSZ8081RNB, in PHY control 2 register (0x1f), Phy is configured for 25Mhz clock mode.

I tried and it is working for me.

Regards

Sharad

[igorpadykov]

Hi Aaron

what bps used in the case, it should work in rmii with ENET2_TX_CLK and

one can look at dts settings in

linux/arch/arm/boot/dts/imx6ull-14x14-evk.dts

linux-imx.git - i.MX Linux Kernel 

test with i.MX6ULL EVK NXP Demo images

https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0_iMX6ULL&appType=license&location=null&Pare... 

Best regards
igor
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[aaronbrice]

That one looks like the imx6ull is providing clock to the phy with ENET2_REF_CLK2.  In my case, I have a 25MHz crystal connected to phy XI/XO, and need to have phy provide clock back to the imx with ENET2_TX_CLK as input.

Thanks,

Aaron

[igorpadykov]

clock direction can be set with GPR1 in arch/arm/mach-imx/mach-imx6ul.c
function imx6ul_enet_clk_init() ,IMX6UL_GPR1_ENET_CLK_DIR

linux-imx.git - i.MX Linux Kernel 

Best regards
igor

[aaronbrice]

Thanks igor.  I had tried that and it didn't work.  Table 22-2 in the i.MX6ULL reference manual says that the ENETn_TX_CLK signals which are affected by GPR1 are only available in MII mode.  Is that correct, you can't input a clock in RMII mode?

[igorpadykov]

ENET2_TX_CLK is used on i.MX6ULL EVK board with rmii phy, one can look on p.11 schematic SPF-28616.

Schematics (1)
Design files, including hardware schematics, Gerbers, and OrCAD files.
MCIMX6ULL-EVK_DESIGNFILES
http://www.nxp.com/products/software-and-tools/software-development-tools/i.mx-software-and-tools/ev...

Best regards
igor

[aaronbrice]

p.11 of SPF-28616 shows ENET2_TX_CLK as an output providing the clock to XI on the phy.  I'm talking about having a crystal connected to XI/XO on the phy, and connecting the phy's REF_CLK to ENET2_TX_CLK as an input to the CPU.

Thanks,

Aaron

[igorpadykov]

REF_CLK with ENET2_TX_CLK as an input to the CPU also allowed configuration.

Best regards
igor