I'm having some trouble understanding the right register to set the QoS priority for the IPUs, as the manual makes it seem like there are two different places (references are to the Quad Plus manual here.)
There's IOMUXC_GPR6 and GPR7 (section 36.4.7-8) which control IPU1 R/W AXI ID QoS priorities.
Then there's the AQoS control registers associated with the IPUs (section 47.3. Actually here the manual lists the IPUs as IPU0 and IPU1, but I'm assuming they meant 1 and 2.) These contain a priority register. The field description is:
P0: In Regulator mode, defines the LOW hurry level. In Fixed/Limiter mode, defines the Urgency level for WRITE transactions.
P1: In Regulator mode, defines the HIGH hurry level. In Fixed/Limiter mode, defines the Urgency level for READ transactions.
So I'm wondering what the difference between the GPR6/7 registers and the AQoS priority registers are. I'm not super experienced with embedded systems, so apologies if the answer is obvious. Thanks for the help!